Alphawave Semi and Keysight Collaboration - PCIe 6.0 64GT/s Interoperability (Graphic: Alphawave Semi)

Alphawave Semi (https://cts.businesswire.com/ct/CT?id=smartlink&url=http%3A%2F%2Fawavesemi.com&esheet=53870867&newsitemid=20231214947029&lan=en-US&anchor=Alphawave+Semi&index=1&md5=2a6c5da64d9a589b2d62b9b919460f60) (LSE: AWE), a global leader in high-speed connectivity for the world’s technology infrastructure, today announced successful collaboration with Keysight Technologies, a market-leading design, emulation, and test solutions provider, demonstrating interoperability between Alphawave Semi’s PCIe 6.0 64 GT/s Subsystem (PHY and Controller) Device and Keysight PCIe 6.0 64 GT/s Protocol Exerciser, negotiating a link to the maximum PCIe 6.0 data rate. Alphawave Semi, already on the PCI-SIG 5.0 Integrators list, is accelerating next-generation PCIe 6.0 Compliance Testing through this collaboration.

Alphawave Semi’s leading-edge silicon implementation of the new PCIe 6.0 64 GT/s Flow Control Unit (FLIT)-based protocol enables higher data rates for hyperscale and data infrastructure applications. Keysight and Alphawave Semi achieved another milestone by successfully establishing a CXL 2.0 link setting the stage for future cache coherency in the datacenter.

“Test and measurement are critical aspects to interoperability, enabling Alphawave Semi to bring our products and customer solutions to market faster,” said Letizia Giuliano, Vice President of IP Product Marketing at Alphawave Semi. “We are excited about our collaboration with Keysight, which speeds up the transition to 64 GT/s through Keysight’s state-of-the-art PCIe 6.0 protocol validation solution and instills confidence in our ability to consistently provide connectivity solutions that accelerate AI processing in high-performance computing and data infrastructure.”

“In the race to scale AI, PCIe will play a pivotal role in connecting compute resources and efficiently handling required workloads. This collaboration with Alphawave Semi demonstrates the commitment of both companies to the development of PCIe 6.0 standard anticipating the high-performance computing demands driven by advancements in AI and ML,” said Dr. Joachim Peerlings, Vice President of Network and Data Center Solutions at Keysight. “This will unlock a new era of connectivity addressing the massive surge in I/O performance needed for compute-intensive applications like generative AI.”

PCIe 6.0 marks the evolution of the ubiquitous technology from two-level NRZ to four-level PAM4 signaling. While this transition introduces signal integrity and new protocol challenges to ensure essential backward compatibility, it enhances the technology's futureproofing through the implementation of Forward Error Correction (FEC) via FLIT. FEC allows for a higher bit error rate (BER) tolerance while still delivering an acceptable packet loss. This collaboration resulted in the successful demonstration of FLIT-mode transactions (requests and completions) of payload FLITs on the silicon implementation of the PCIe 6.0 64 GT/s subsystem.

The Alphawave Semi PCIe subsystem is an extremely power-efficient, low-latency, and highly reliable interface IP, having been built off the industry’s most successful PAM4 SerDes IP. In AI and high-performance computing (HPC) systems where memory performance is key, the Alphawave Semi PCIe 6.0 Subsystem can be expanded to support CXL 3.0 with a PCIe and CXL Controller and enable memory coherency at the data center level.